Generally, a NOR-type flash memory adopts a common source method. In other words, there a contact is typically formed in every 16 cells and the source lines of the 16 cells are connected to form an N+ type diffusion layer. For a design rule of 0.25 μm class or smaller than 0.18 μm class, most semiconductor devices are adopting shallow trench isolation (STI) as a device isolation method. Flash memory devices, smaller than 0.35 μm class are adopting a self-aligned source (SAS) technique to reduce cell size.
These known techniques (e.g., STI and SAS) are described in detail below. FIG. 1a illustrates a top or plan view of a flash memory cell fabricated without employing the SAS technique. FIG. 1b illustrates the top view of a flash memory cell fabricated by employing the SAS technique. Referring to FIGS. 1a and 1b, a flash memory cell typically comprises a common source line 2, a gate 6, a device isolation area 8, i.e., a STI area, a drain contact 10, a bit line 9; and a gap 4 between the gate 6 and the common source line 2.
As shown in FIGS. 1a and 1b, the SAS technique can reduce cell size by forming the common source line 6 under the gap 4 and, therefore, is a valuable process in 0.25 μm technology. The SAS technique enables about a 20% reduction in the cell size of a flash memory.
FIG. 2 illustrates the top view of a flash memory cell array manufactured without employing the SAS technique. The flash memory cells have a drain contact 10 and are connected through a series of common source lines 2, that are vertical to the bit line 9.
FIG. 3a illustrates the top view of a flash memory cell array manufactured by employing the SAS technique. FIG. 3b is a cross-sectional view of FIG. 3a taken along the line a–a′. As shown in FIGS. 3a and 3b, in case of a flash memory adopting the SAS technique, a plurality of trench areas 8a are formed in parallel with the bit line 9 and ions are implanted into the trench areas 8a and active regions 1 to form the common source line 2. The common source line 2 has roughly a shape of square wave in a cross-sectional view. The trench areas 8a are filled with oxide by means of high density plasma to form the STI 8.
Here, as shown in FIG. 3b, the resistance per cell tends to increase abruptly because the common source line 2 is formed along the surface of the trench areas 8a and the active regions 1. The resistance of the common source line 2 increases because an actual surface area is enlarged due to junction resistance generated along the surface of the trench areas 8a, as shown in FIG. 3b, and because the resistivity of the sidewalls of the trench areas 8a also increases. In other words, during diffusion or ion implantation, relatively fewer ions are implanted into the sidewalls of the trench areas 8a and, therefore, resistance increases abruptly.
FIG. 4 illustrates a schematic diagram of a flash memory employing the common source line shown in FIG. 3a. As shown in FIG. 4, if the resistance per cell increases, each cell has a different value of back bias due to IR drop between the first cell and the eighth cell because a source contact is formed every 16 cells. Therefore, an error may occur when a flash memory performs a read operation. In particular, because the flash memory uses an internal high voltage, trench areas become deeper as cell size is reduced, thereby acting adversely on source resistance.
Table 1 shows IR drop of each cell when source resistance is 600Ω per cell. As shown in Table 1, voltages between the first and the eighth cells differ as much as 0.06 V, indicating that current difference occurs due to Vds (voltage difference between a source and a drain) difference between cells. Here, resistance means a source resistance of a cell.
TABLE 1FirstSecondThirdFourthFifthSixthSeventhEighthNinthcellcellcellcellcellcellcellcellcell123456789Left60012001800240030003600420048005400resistanceRight960090008400780072006600600054004800resistanceTotal564.71058.81482.41835.32117.62329.42470.62541.22541.2resistanceIR drop0.0170.0320.0440.0550.0640.0700.0740.0760.076
FIG. 5 is a graph illustrating a value of source resistance according to the depth of a trench area. If a trench area is about 2400 Å in depth, resistance per cell is 600Ω. If a trench area is about 3600 Å in depth, resistance per cell is 880Ω, a 50% increase in comparison to 2400 Å. A 0.18 μm class flash memory has the 3500 Å depth of the trench area, which causes a pernicious effect on source resistance of a cell region. To solve this problem, a method of forming trench areas with different depth has been proposed. In a flash memory according to this conventional fabrication method, the depths of the trench areas are about 3500 Å in a peripheral region and about 1800 Å in a cell region. However, the conventional method may complicate the fabrication process and cause overlay because the cell region and the peripheral region have to be separately masked and etched.